1. Field of the Invention
The invention relates to a data processing apparatus, and more particularly to a micro-processor having a bus interface function.
2. Description of the Related Art
A cache memory may be incorporated into a micro-processor for enhancing system performances. Such a micro-processor including a cache memory therein can accomplish its maximum performance when the cache memory is hit, but would have performances the same as or inferior to performances of a system including no cache memory, when the cache memory is incorrectly hit. In particular, it is necessary in a system carrying out real-time control to estimate a process time on the assumption that a memory access performance is at a minimum. Hence, if such a system has to carry out irregular process such as interruption, a hit rate of a cache memory cannot avoid from being reduced, resulting in reduction in performances due to cachexe2x80x94replace.
In a system for carrying out real-time control, there are increased applications which require multi-media processing such as image processing and audio processing. Thus, there is increased a demand for a micro-processor which can carry out both real-time control and data processing. Hence, a system for carrying out real-time control, including no cache memory, is also required to enhance capability of making access to an external memory, an external device, and so on. As a function for enhancing access performance, here is known a burst transfer function.
A pre-fetch queue FIFO 101 fetches and stores therein a command code. A pre-fetch queue valid 103 indicates that an effective command code is stored in the pre-fetch queue FIFO 101. A queue clear signal 104 is generated when a branch command or interruption is to be carried out, and is transmitted to the pre-fetch queue valid 103.
A pre-fetch request signal 107 is transmitted from OR circuit 105 to an access priority judging circuit 111. The pre-fetch request signal 107 is made active when the pre-fetch queue FIFO 101 has a vacancy therein. A queue empty signal 108 is transmitted from an inverter 106 to the access priority judging circuit 111. The queue empty signal 108 is made active when the pre-fetch queue FIFO 101 is entirely empty. An operand data request signal 109 is transmitted to the access priority judging circuit 111. The operand data request signal 109 is made active when operand data access 109a is generated.
The access priority judging circuit 111 determines a kind of access to be generated next. A bus state control circuit 122 generates a bus state in accordance with access having been determined by the access priority judging circuit 111.
The bus state control circuit 122 transmits a bus state signal, a T1 state signal and a T2 state signal to a bus timing producing circuit 126 in accordance with bus access signals 123, 124 and 125. The T1 state signal first outputs an address and a control signal. The T2 state signal makes access to a memory, a device and so on, following the T1 state signal.
The bus state control circuit 122 transmits a priority judging signal 116 to the access priority judging circuit 111. The priority judging signal 116 is a timing signal for judging a priority of next address.
The bus timing producing circuit 126 generates bus timing signals 127 and 128 in accordance with the T1 and T2 state signals 123 and 124 transmitted from the bus state control circuit 122.
As illustrated in FIG. 2, a micro-processor 150 including therein a bus interface having such a structure as illustrated in FIG. 1 and having been explained above is connected to both a first memory 151 and a second memory 152 through a system bus 153. The first memory 151 has a function of carrying out burst transfer and stores therein a command code. The second memory 152 makes operand data access. For instance, the first memory 151 may be constituted as a read only memory (ROM) having a paging function, or as a synchronous FLASH memory, and the second memory 152 may be constituted as SRAM or DRAM.
Hereinbelow is explained an operation of the above-mentioned bus interface illustrated in FIG. 1.
When a program is to be carried out in branch, the pre-fetch queue valid 103 is made entirely invalid by means of the queue clear signal 104, and queue empty signal 108 is made active.
The access priority judging circuit 111 determines a kind of bus access on receipt of the priority judging signal 116, and transmits a command fetch access signal 113 or an operand data access signal 114 to the bus stat control circuit 122. The access priority judging circuit 111 activates the operand data access signal 114 when both the pre-fetch request signal 107 and the operand data request signal 109 are received. As an alternative, the access priority judging circuit 111 may be designed to activate the command fetch access signal 113 when the queue empty signal 108 is active.
The bus state control circuit 122 transmits the T1 state signal, the T2 state signal and the bus state signal to the bus timing generating circuit 126 in accordance with the bus access signals 123, 124 and 125. The bus timing generating circuit 126 makes access to external ROM or RAM, and carries out command fetch access or operand data access.
In burst transfer, there is first generated a state (hereinafter, referred to as xe2x80x9cT1 statexe2x80x9d) for outputting an address, a control signal and so on, and subsequently is generated a state (hereinafter, referred to as xe2x80x9cT2 statexe2x80x9d) for making access to a memory, a device and so on. If a memory or device fulfills a requirement for carrying out burst transfer when access is to be made to successive addresses in the same memory, only T2 state is generated for making access to the later address. That is, it would be possible to accomplish high-speed memory access in burst transfer, since T1 state is not generated in the second or later access in successive access.
Time necessary for generating T1 or T2 state is dependent on a specific memory. As an example of a memory having a function of burst transfer, there is a memory which makes use of successive high-speed access to a memory cell associated with a selected address, or a memory having a interleave structure.
In general, a micro-processor carries out a command through the steps of (a) making access to a memory for fetching a command code, (b) storing the command code in a pre-fetch queue, (c) data-aligning the command code, and (d) decoding the command code to thereby identify a command, and carrying out the thus identified command. A micro-processor further carries out the step of (e) making access to a memory for writing data thereinto or reading data out thereof, when a specific command is to be carried out.
In the above-mentioned steps, access to a memory in the step (a) for fetching a command code is called command fetch access, and access to a memory in the step (e) for writing data thereinto or reading data out thereof is called operand data access.
In accordance with command fetch access, since access is to be made successively in an order of address except branching, it would be possible to accomplish high-speed access in burst transfer through the use of a memory having a function of carrying out burst transfer.
On the other hand, operand data access is characterized in that address is seldom successive except that block transfer is to be carried out, and that an interval between addresses is not constant.
Comparing a priority of command fetch access to a priority of operand data access, operand data access has a higher priority. Hence, if a request of operand data access is made while burst transfer of command fetch is being carried out, the burst transfer is interrupted, and operand data access is carried out.
In the conventional micro-processor, if an operand data request 109 is made to another memory while command fetch of T1, T2, T2, T2, - - - are successively made access in burst transfer, the burst transfer is interrupted, and operand data access is carried out. Thereafter, command fetch is made to restart. First memory access after restarting this command fetch is T1 and T2, and accordingly, it is not possible to carry out burst transfer starting from T2 state.
Hence, if burst transfer of command fetch is automatically interrupted when an operand data request 109 is made, burst transfer of command fetch is frequently interrupted in accordance with a frequency at which operand data access is to be made, resulting in a problem that transfer capability by burst transfer cannot be adequately drawn out.
In particular, since operand data access is seldom successively made, and an interval between operand data accesses is not constant, it would occur that command fetch and operand data are alternately accessed, resulting in high possibility that advantageous effects of burst transfer cannot be obtained.
In general, burst transfer is completed when burst transfer reaches a certain condition, and then, access starts to be made again from T1 state. For instance, when a memory having a function of burst transfer or a memory having a function of paging at a high speed is employed, the number of burst transfer may be determined in advance on the basis of a structure of an employed memory, or burst transfer may be completed at a word boundary or at a half-word boundary. In such a case, if an operand data request 109 is made immediately before an access is made to a memory which access is earlier by one than a boundary condition at which burst transfer of command fetch is completed, the burst transfer of command fetch is interrupted, and operand data access is carried out. Then, command fetch access earlier by one than the boundary condition at which burst transfer is completed is carried out from T1 state, and thereafter, command fetch access at the boundary condition at which burst transfer is completed is carried out from T1 state. As a result, there is caused a problem that burst transfer of command fetch is interrupted in an access immediately before the boundary condition, and an access is restarted twice in sequence from T1 state, which makes it impossible to draw out transfer capability of a bus interface.
In addition, contrary to burst transfer of command fetch, a micro-processor which, on receipt of the queue empty signal 108 while operand data access is being carried out in burst transfer, interrupts the burst transfer by the queue empty signal 108, and carries out command fetch access is also accompanied with a problem that first access to a memory, to be made when operand data access is restarted, starts only from T2 state. Accordingly, if burst transfer of operand data access is automatically interrupted when the queue empty signal 108 is transmitted, burst transfer of operand data access may be interrupted, which would make it impossible to draw out transfer capability of a bus interface.
Japanese Unexamined Patent Publication No. 64-72254 has suggested a data processing apparatus comprised of a data buffer for temporarily storing data therein, means for managing an amount of data stored in the data buffer, and a burst register for setting the number of successive data transfer. The number of successive data transfer in a single data-transfer sequence is determined in accordance with an amount of data stored in the data buffer, and the thus determined number is set in the burst register.
Japanese Unexamined Patent Publication No. 62-80753 has suggested a bus controller in which a plurality of controllers are commonly used for data transfer, and use of the controllers is managed by a managing device. The managing device includes a circuit which assigns priority to transfer request signals transmitted from the controllers, and allows the controller to which top priority is assigned, to use a common bus while the transfer request signal is being transmitted. At least one of the controllers has two lines in which a transfer request signal is transmitted, and alternately turns a transfer request signal on or off in every data transfer. The managing device allows a controller having second top priority to use a common bus when the transfer request signal is switched.
Japanese Unexamined Patent Publication No. 6-274450 has suggested a data transfer system including CPU which transmits and receives data in single transfer in which data associated with one address is transferred at a time, a bus which transfers data in burst transfer in which data associated with a plurality of successive addresses is transferred at a time, a data reader which is electrically connected to the bus, and reads data out of the bus in burst transfer, an address transmitter which is electrically connected between CPU and the bus, and transmits an address to the data reader through the bus, which address corresponds to one of addresses transmitted from CPU for reading data, a transfer buffer which temporarily stores data having been read out of the data reader through the bus in burst transfer on the basis of the address transmitted from CPU, and means for reading data stored in the transfer buffer, in accordance with the addresses transmitted from CPU, and transferring the data to CPU in single transfer.
Japanese Unexamined Patent Publication No. 5-89031 has suggested a micro-processor which makes access to a device in a bus cycle comprising a first state for preparation of access of a device and a second state for allowing a device to make access. The micro-processor is comprised of a decoder for detecting a command to access successive addresses and decoding the addresses, an indicator for indicating that a bus cycle to be carried out is successive addresses, a detector for detecting as to whether the device is able to successively access, and a controller which successively carries out device access through a first bus cycle comprising both the first and second states and second or later bus cycle consisting of the second state, in accordance with an instruction transmitted from the indicator.
Japanese Unexamined Patent Publication No. 6-208540 has suggested a bus master module device including a direct memory access controller which ceases using a system bus at a predetermined timing while burst transfer is being carried out by occupying the system bus, and allows other module to occupy the system bus, a masking circuit which detects that the system bus is ceased to use by the direct memory access controller, and interrupts a path through which an allowance for using the system bus is supplied, before the direct memory access controller is allowed again to use the system bus, and a sensing circuit which transmits a signal to the other module, indicating that masking has been completed by the masking circuit.
The above-mentioned problems remain unsolved even by the above-mentioned Japanese Publications.
Hence, in view of the above-mentioned problems, it is an object of the present invention to provide a micro-processor having a function of bus interface, which is capable of suppressing interruption of burst transfer of command fetch, reducing overhead of T1 state which is generated when command fetch is restarted to carry out after operand data access has been carried out, and resultingly enhancing capability in data transfer in a bus interface.
It is also an object of the present invention to provide a micro-processor having a function of bus interface, which is capable of suppressing interruption of burst transfer in a cue empty signal, reducing overhead of T1 state which is generated when operand data access is restarted to carry out after command fetch access has been carried out, and resultingly enhancing capability in data transfer in a bus interface.
In one aspect of the present invention, there is provided a micro-processor including (a) a pre-fetch queue FIFO which fetches and stores therein a command code, (b) a pre-fetch queue valid indicating that an effective command code is stored in the pre-fetch queue FIFO, (c) an access priority judging circuit receiving a pre-fetch request signal indicating that there is a vacancy in the pre-fetch queue FIFO, a queue empty signal indicating that the pre-fetch queue FIFO is entirely empty, and an operand data request signal indicating that there has been generated an operand data access, and determining a kind of next bus access, (d) a bus state control circuit transmitting a bus interface signal, based on the kind of next bus access having been determined by the access priority judging circuit, and also transmitting a burst transfer signal indicating that a memory is in a condition for carrying out burst transfer, and (e) an access register storing data about the previous bus access, the access priority judging circuit taking a command fetch access in preference to an operand data access in the next bus access when data stored in the access register is a command fetch access, and the pre-fetch request signal, the operand data request signal, and the burst transfer signal are all transmitted.
The micro-processor may further include (f) a first register storing a condition at which burst transfer of a command fetch is completed, and (g) a first comparator receiving the next command fetch address and the condition transmitted from the first register to thereby detect a boundary condition of a memory, and transmitting a first signal indicating that burst transfer should be completed, as a result of detecting the boundary condition, the access priority judging circuit making judgement as to whether a command fetch access should be taken preference over an operand data access in the next bus access in accordance with the first signal, when data stored in the access register is a command fetch access, and the pre-fetch request signal, the operand data request signal, and the burst transfer signal are all transmitted.
The micro-processor may further include (h) a first counter counting the number of burst transfer, (i) a second register storing the number of burst transfer in a command fetch, and (j) a second comparator comparing the number of burst transfer counted by the first counter to the number of burst transfer stored in the second register, and transmitting a second signal indicating that burst transfer should be completed, as a result of comparison, the access priority judging circuit making judgement as to whether a command fetch access should be taken preference over an operand data access in the next bus access in accordance with the second signal, when data stored in the access register is a command fetch access, and the pre-fetch request signal, the operand data request signal, and the burst transfer signal are all transmitted.
The micro-processor may further include (k) a detector detecting that a command code in the pre-fetch queue FIFO is smaller than a predetermined amount, on the basis of the pre-fetch queue valid, and transmitting a third signal indicating that burst transfer should be completed, as a result of detection, the access priority judging circuit making judgement as to whether a command fetch access should be taken preference over an operand data access in the next bus access in accordance with the third signal, when data stored in the access register is a command fetch access, and the pre-fetch request signal, the operand data request signal, and the burst transfer signal are all transmitted.
The micro-processor may further include (l) a second counter counting the number of burst transfer, (m) a third register storing the number of burst transfer in operand data access, and (n) a third comparator comparing the number of burst transfer counted by the second counter to the number of burst transfer stored in the third register, and transmitting a fourth signal indicating that burst transfer should be completed, as a result of comparison, the access priority judging circuit giving first priority to the cue empty signal, second priority to the operand data request signal, and third priority to the pre-fetch request signal, respectively, the access priority judging circuit making judgement as to whether an operand data access should be taken preference over a command fetch access in the next bus access in accordance with the fourth signal, when data stored in the access register is an operand data access, and the cue empty signal, the operand data request signal, and the burst transfer signal are all transmitted.
The micro-processor may further include (o) a fourth register storing a condition at which burst transfer in operand data is completed, and (p) a fourth comparator receiving the next operand data address and the condition transmitted from the fourth register to thereby detect a boundary condition of a memory, and transmitting a fifth signal indicating that burst transfer should be completed, as a result of detecting the boundary condition, the access priority judging circuit giving first priority to the cue empty signal, second priority to the operand data request signal, and third priority to the pre-fetch request signal, respectively, the access priority judging circuit making judgement that the next bus address is operand data access in accordance with the fifth signal, when data stored in the access register is an operand data access, and the cue empty signal, the operand data request signal, and the burst transfer signal are all transmitted.
There is further provided a micro-processor having a bus interface function, the micro-processor determining a priority of a bus access, based on data about a kind of the previous bus access, data about a condition at which burst transfer of the next bus access can be carried out, and data about a condition at which the number of burst transfer reaches a predetermined number.
There is still further provided a micro-processor having a bus interface function, the micro-processor, if pre-fetch cue makes a request to carry out burst transfer while burst transfer of operand data access is being carried out, keeps the request pending until the burst transfer of operand data access is completed.
There is yet further provided a micro-processor including (a) a bus interface in which a request of operand data is given a higher priority than a request of command fetch, (b) an access register storing data about the previous access, the micro-processor, if a request of operand data is made while burst transfer access for command fetch is being carried out, determining whether burst transfer should be interrupted or continued, based on data stored in the access register.
It is preferable that the micro-processor takes command fetch access in preference to operand data access, while a first signal is being transmitted which first signal indicates that a memory is put in such a condition that burst transfer of the next access can be carried out.
There is further provided a micro-processor including (a) a bus interface in which a request of operand data is given a higher priority than a request of command fetch, (b) an access register storing data about the previous access, the micro-processor, if a request of operand data is made while burst transfer access for command fetch is being carried out, taking command fetch access in preference to operand data access until a first or second signal is transmitted, the first signal indicating that a memory is put in such a condition that burst transfer of the next access can be carried out, the second signal indicating that burst transfer should be completed.
There is further provided a micro-processor including (a) a bus interface in which a request of operand data is given a higher priority than a request of command fetch, (b) an access register storing data about the previous access, the micro-processor, if a request of operand data is made while burst transfer access for command fetch is being carried out, taking command fetch access in preference to operand data access when first and second signals are transmitted, the first signal indicating that a memory is put in such a condition that burst transfer of the next access can be carried out, the second signal indicating that burst transfer should be completed.
In another aspect of the present invention, there is provided a method of driving a micro-processor, including the step of taking command fetch access in preference to operand data access in the next bus access, when the following conditions are all fulfilled: (a) the previous bus access is command fetch access; (b) there is a vacancy in pre-fetch queue FIFO; (c) there is generated operand data access; and (d) a memory is in such a condition that burst transfer can be carried out.
There is further provided a method of driving a micro-processor, including the steps of (a) storing a condition at which burst transfer of command fetch is completed, (b) detecting a boundary condition of a memory, based on the next command fetch address and the condition, and (c) judging whether command fetch access should be taken preference over operand data access in the next bus access in accordance with a result of detection carried out in the step (b), when the above-mentioned conditions are all fulfilled.
There is still further provided a method of driving a micro-processor, including the steps of (a) counting the number of burst transfer, (b) storing the number of burst transfer in command fetch, (c) comparing the number in the step (a) to the number in the step (b), and (d) judging whether command fetch access should be taken preference over operand data access in the next bus access in accordance with a result of comparison carried out in the step (c), when the above-mentioned conditions are all fulfilled.
There is yet further provided a method of driving a micro-processor, including the steps of (a) detecting an amount of command code in pre-fetch queue FIFO, (b) judging whether command fetch access should be taken preference over operand data access in the next bus access, if the amount of command code is smaller than a predetermined amount, and if the above-mentioned conditions are all fulfilled.
There is further provided a method of driving a micro-processor, including the step of determining a priority of a bus access, based on data about a kind of the previous bus access, data about a condition at which burst transfer of the next bus access can be carried out, and data about a condition at which the number of burst transfer reaches a predetermined number.
There is further provided a method of driving a micro-processor, including the step of, if pre-fetch cue makes a request to carry out burst transfer while burst transfer of operand data access is being carried out, pending the request until the burst transfer of operand data access is completed.
There is further provided a method of driving a micro-processor, including the steps of (a) giving a priority to a request of operand data over a request of command fetch, (b) storing data about the previous access, and (c) if a request of operand data is made while burst transfer access for command fetch is being carried out, determining whether burst transfer should be interrupted or continued, based on data stored in the access register.
It is preferable that command fetch access is taken preference over operand data access in the step (c), while a first signal is being transmitted which first signal indicates that a memory is put in such a condition that burst transfer of the next access can be carried out.
There is further provided a method of driving a micro-processor, including the steps of (a) giving a priority to a request of operand data over a request of command fetch, (b) storing data about the previous access, and (c) if a request of operand data is made while burst transfer access for command fetch is being carried out, taking command fetch access in preference to operand data access until a first or second signal is transmitted, the first signal indicating that a memory is put in such a condition that burst transfer of the next access can be carried out, the second signal indicating that burst transfer should be completed.
There is further provided a method of driving a micro-processor, including the steps of (a) giving a priority to a request of operand data over a request of command fetch, (b) storing data about the previous access, and (c) if a request of operand data is made while burst transfer access for command fetch is being carried out, taking command fetch access in preference to operand data access when first and second signals are transmitted, the first signal indicating that a memory is put in such a condition that burst transfer of the next access can be carried out, the second signal indicating that burst transfer should be completed.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.